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1 `timescale 1ns/1ns
2 // program declaration with ports.
3 program clocking_skew_prg (
4 input wire clk,
5 output logic [7:0] din,
6 input wire [7:0] dout,
7 output logic [7:0] addr,
8 output logic ce,
9 output logic we
10 );
11
12 // Clocking block
13 default clocking ram @(posedge clk);
14 input #1 dout;
15 output #1 din,addr,ce,we;
16 endclocking
17
18 initial begin
19 // Init the outputs
20 ram.addr <= 0;
21 ram.din <= 0;
22 ram.ce <= 0;
23 ram.we <= 0;
24 // Write Operation to Ram
25 for (int i = 0; i < 2; i++) begin
26 // Below line is same as repeat (2) @ (posedge clk);
27 ## 2 ;
28 ram.addr <= i;
29 ram.din <= $random;
30 ram.ce <= 1;
31 ram.we <= 1;
32 ## 2;
33 ram.ce <= 0;
34 end
35 // Read Operation to Ram
36 for (int i = 0; i < 2; i++) begin
37 // Below line is same as @ (posedge clk);
38 ## 1 ;
39 ram.addr <= i;
40 ram.ce <= 1;
41 ram.we <= 0;
42 // Below line is same as repeat (3) @ (posedge clk);
43 ## 3;
44 ram.ce <= 0;
45 end
46 #40 $finish;
47 end
48
49 endprogram
50
51 // Simple top level file
52 module clocking_skew();
53
54 logic clk = 0;
55 wire [7:0] din;
56 logic [7:0] dout;
57 wire [7:0] addr;
58 wire ce;
59 wire we;
60 reg [7:0] memory [0:255];
61
62 // Clock generator
63 always #10 clk++;
64
65 // Simple ram model
66 always @ (posedge clk)
67 if (ce)
68 if (we)
69 memory[addr] <= din;
70 else
71 dout <= memory[addr];
72
73 // Monitor all the signals
74 initial begin
75 $monitor("@%0dns addr :%0x din %0x dout %0x we %0x ce %0x",
76 $time, addr, din,dout,we,ce);
77 end
78 // Connect the program
79 clocking_skew_prg U_program(
80 .clk (clk),
81 .din (din),
82 .dout (dout),
83 .addr (addr),
84 .ce (ce),
85 .we (we)
86 );
87
88 endmodule
You could download file clocking_hash.sv here
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