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1 `timescale 1ns/1ns
2 // program declaration with ports.
3 program clocking_hier_prg (
4 input wire clk,
5 output logic [7:0] din,
6 input wire [7:0] dout,
7 output logic [7:0] addr,
8 output logic ce,
9 output logic we
10 );
11
12 // Clocking block
13 clocking ram @(posedge clk);
14 input #1 dout = clocking_skew.dout;
15 output #1 din,addr,ce,we;
16 endclocking
17
18 initial begin
19 $monitor("@%0dns addr :%0x din %0x dout %0x we %0x ce %0x",
20 $time, addr, din,ram.dout,we,ce);
21 // Init the outputs
22 ram.addr <= 0;
23 ram.din <= 0;
24 ram.ce <= 0;
25 ram.we <= 0;
26 // Write Operation to Ram
27 for (int i = 0; i < 2; i++) begin
28 @ (posedge clk);
29 ram.addr <= i;
30 ram.din <= $random;
31 ram.ce <= 1;
32 ram.we <= 1;
33 @ (posedge clk);
34 ram.ce <= 0;
35 end
36 // Read Operation to Ram
37 for (int i = 0; i < 2; i++) begin
38 @ (posedge clk);
39 ram.addr <= i;
40 ram.ce <= 1;
41 ram.we <= 0;
42 // Below line is same as @ (posedge clk);
43 @ (ram);
44 ram.ce <= 0;
45 end
46 #40 ;
47 end
48
49 endprogram
50
51 // Simple top level file
52 module clocking_skew();
53
54 logic clk = 0;
55 wire [7:0] din;
56 logic [7:0] dout;
57 wire [7:0] addr;
58 wire ce;
59 wire we;
60 reg [7:0] memory [0:255];
61
62 // Clock generator
63 always #10 clk++;
64
65 // Simple ram model
66 always @ (posedge clk)
67 if (ce)
68 if (we)
69 memory[addr] <= din;
70 else
71 dout <= memory[addr];
72
73 // Connect the program
74 clocking_hier_prg U_program(
75 .clk (clk),
76 .din (din),
77 .dout (),
78 .addr (addr),
79 .ce (ce),
80 .we (we)
81 );
82
83 endmodule
You could download file clocking_hier.sv here
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