In Verilog 1995/2001, it is always required to assign the value returned by a function. In SystemVerilog by using following syntax one can avoid assigning a return value to a variable.

void'(call_function(with_params));

  1 module function_discard ();
  2 
  3 bit a ;
  4 
  5 initial begin
  6    #1  void'(doInit(4,5));
  7    #1  void'(doInit(9,6));
  8    #1  $finish;
  9 end
 10 
 11 function bit unsigned doInit (input bit [3:0] count, add); 
 12   automatic reg [7:0] b;
 13   if (count > 5) begin
 14     $display ("@%g Returning from function", $time);
 15     return 0;
 16   end
 17   b = add;
 18   $display ("@%g Value passed is %d", $time, count + b);
 19   doInit = 1;
 20 endfunction
 21 
 22 endmodule

 @1 Value passed is   9
 @2 Returning from function

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