|
|
In Verilog 2001 and 1995, module declaration inside another module is not allowed, only modules can be instanciated. But in SystemVerilog, module declaration can be nested.The outer name space is visible to the inner module so that any name declared there can be used, unless hidden by a local name, provided the module is declared and instantiated in the same scope. |
|
|
1 //+++++++++++++++++++++++++++++++++++++++++++++++++
2 // Nested Module
3 //+++++++++++++++++++++++++++++++++++++++++++++++++
4 module nested_module();
5
6 //=================================================
7 // Module declration inside the module
8 //=================================================
9 module counter(input clk,enable,reset,
10 output logic [3:0] data);
11
12 always @ (posedge clk)
13 if (reset) data <= 0;
14 else if (enable) data ++;
15 endmodule
16
17 logic clk = 0;
18 always #1 clk++;
19 logic enable, reset;
20 wire [3:0] data;
21
22 counter U(clk,enable,reset,data);
23
24 initial begin
25 $monitor("@%0dns reset %b enable %b data %b",
26 $time,reset,enable,data);
27 reset <= 1;
28 #10 reset <= 0;
29 #1 enable <= 1;
30 #10 enable <= 0;
31 #4 $finish;
32 end
33
34 endmodule
You could download file nested_module.sv here
|
