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1 module expect_assertion;
2
3 logic clk = 0;
4 always #1 clk ++;
5
6 logic a, b,c;
7
8 default clocking myclk @ (posedge clk);
9
10 endclocking
11
12 initial begin
13 a <= 0;
14 b <= 0;
15 c <= 0;
16 ##1 ;
17 a <= 1;
18 ##1 ;
19 a <= 0;
20 b <= 1;
21 ##1 ;
22 b <= 0;
23 c <= 0;
24 ##1 ;
25 c <= 0;
26 ##20000 $finish;
27 end
28
29 initial begin
30 ##1 ;
31 // Wait for the sequence if pass, terminate sim
32 expect ( @ (posedge clk) a ##1 b ##1 c ##1 ! c)
33 $finish;
34 else
35 $error ("Something is wrong");
36 end
37
38 endmodule
You could download file expect_assertion.sv here
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