1 `timescale 1ns / 1ns
  2 // Verilog DUT 
  3 module counter(
  4 rst,   // Reset input
  5 clk,   // Clock Input
  6 d_out  // Counter output
  7 );
  8 // Port Declation
  9 input      rst;
 10 input      clk;
 11 output  [31:0]  d_out;
 12 // Internal data type
 13 reg  [31:0]  d_out;
 14 // Code starts here
 15 always @ (posedge clk)
 16   if (rst) d_out <= 0;
 17   else d_out <= d_out + 1;
 18 
 19 endmodule
 20 // Testbench top level
 21 module tb();
 22 reg      rst;
 23 reg      clk;
 24 wire  [31:0]  d_out;
 25 
 26 initial begin
 27  $sc_counter(clk, d_out, rst);// Testbench Connection
 28  clk = 0;
 29 end
 30 // Clock generator
 31 always  #1  clk = ~clk;
 32 // DUT connection
 33 counter dut (
 34     // Inputs
 35     rst,
 36     clk,
 37     // Outputs
 38     d_out
 39 );
 40 
 41 endmodule

  1 #ifndef COUNTER_H
  2 #define COUNTER_H
  3 
  4 #include "systemc.h"
  5 
  6 SC_MODULE (counter) {
  7   sc_in<bool>          clk;   // clock input
  8   sc_out<bool>         rst;   // reset ouput
  9   sc_in<sc_uint<32> >  d_out; // data input
 10   sc_out<int>          done;  // Terminate sim       
 11 
 12   void cnt_model ();
 13   void monitor   ();
 14   void test      ();
 15 
 16   sc_uint<32>  cnt; // counter model
 17   int error; // Error status
 18 
 19   SC_CTOR(counter) {
 20     SC_CTHREAD(monitor,clk.pos());
 21     SC_CTHREAD(cnt_model,clk.pos());
 22     SC_CTHREAD(test,clk.pos());
 23   }
 24 };
 25 
 26 #endif

  1 #include "counter.h"
  2 
  3 // Counter model
  4 void counter::cnt_model() {
  5   while (true) {
  6     wait();
  7     if (rst.read()) {
  8       cnt = 0;
  9     } else {
 10       cnt ++;
 11     }
 12   }
 13 }
 14 // Counter montitor
 15 void counter::monitor() {
 16   error = 0;
 17   while (true) {
 18     wait();
 19     cout << "@" <<sc_time_stamp() << "Counter Monitor : tb "
 20        << cnt << " dut " << d_out << endl;
 21     if (rst.read() == 0) {
 22        if (cnt  ! = d_out) {
 23          error ++;
 24        }
 25     }
 26   }
 27 }
 28 // Counter stim gen
 29 void counter::test() {
 30   done = 0;
 31   while (true) {
 32     rst = true;
 33     cout<<"@"<<sc_time_stamp()<<" Asserting Reset " << endl;
 34     wait(10);
 35     rst = false;
 36     cout<<"@"<<sc_time_stamp()<<" De-asserting Reset " << endl;
 37     wait(20);
 38     // Request for simulation termination
 39     if (error > 0) {
 40       cout << "=======================================" << endl;
 41       cout << " SIMULATION FAILED" << endl;
 42       cout << "=======================================" << endl;
 43     } else {
 44       cout << "=======================================" << endl;
 45       cout << " SIMULATION PASSED" << endl;
 46       cout << "=======================================" << endl;
 47     }
 48     done = 1;
 49     // Just wait for few cycles
 50     wait(100);
 51   }
 52 }

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