1 -------------------------------------------------------
  2 -- Design Name : encoder_using_if
  3 -- File Name   : encoder_using_if.vhd
  4 -- Function    : Encoder using If
  5 -- Coder       : Deepak Kumar Tala (Verilog)
  6 -- Translator  : Alexander H Pham (VHDL)
  7 -------------------------------------------------------
  8 library ieee;
  9     use ieee.std_logic_1164.all;
 10 
 11 entity encoder_using_if is
 12     port (
 13         enable     :in  std_logic;                     --  Enable for the encoder
 14         encoder_in :in  std_logic_vector (15 downto 0);--  16-bit Input
 15         binary_out :out std_logic_vector (3 downto 0)  --  4 bit binary Output
 16 
 17     );
 18 end entity;
 19 
 20 architecture behavior of encoder_using_if is
 21 
 22 begin
 23     process (enable, encoder_in) begin
 24         binary_out <= "0000";
 25         if (enable = '1') then
 26             if (encoder_in = X"0002") then binary_out <= "0001"; end if;
 27             if (encoder_in = X"0004") then binary_out <= "0010"; end if;
 28             if (encoder_in = X"0008") then binary_out <= "0011"; end if;
 29             if (encoder_in = X"0010") then binary_out <= "0100"; end if;
 30             if (encoder_in = X"0020") then binary_out <= "0101"; end if;
 31             if (encoder_in = X"0040") then binary_out <= "0110"; end if;
 32             if (encoder_in = X"0080") then binary_out <= "0111"; end if;
 33             if (encoder_in = X"0100") then binary_out <= "1000"; end if;
 34             if (encoder_in = X"0200") then binary_out <= "1001"; end if;
 35             if (encoder_in = X"0400") then binary_out <= "1010"; end if;
 36             if (encoder_in = X"0800") then binary_out <= "1011"; end if;
 37             if (encoder_in = X"1000") then binary_out <= "1100"; end if;
 38             if (encoder_in = X"2000") then binary_out <= "1101"; end if;
 39             if (encoder_in = X"4000") then binary_out <= "1110"; end if;
 40             if (encoder_in = X"8000") then binary_out <= "1111"; end if;
 41         end if;
 42     end process;
 43 end architecture;

  1 -------------------------------------------------------
  2 -- Design Name : encoder_using_case
  3 -- File Name   : encoder_using_case.vhd
  4 -- Function    : Encoder using Case
  5 -- Coder       : Deepak Kumar Tala (Verilog)
  6 -- Translator  : Alexander H Pham (VHDL)
  7 -------------------------------------------------------
  8 library ieee;
  9     use ieee.std_logic_1164.all;
 10 
 11 entity encoder_using_case is
 12     port (
 13         enable     :in  std_logic;                     --  Enable for the encoder
 14         encoder_in :in  std_logic_vector (15 downto 0);--  16-bit Input
 15         binary_out :out std_logic_vector (3 downto 0)  --  4 bit binary Output
 16 
 17     );
 18 end entity;
 19 
 20 architecture behavior of encoder_using_case is
 21 
 22 begin
 23     process (enable, encoder_in) begin
 24         if (enable = '1') then
 25             case (encoder_in) is
 26                 when X"0002" => binary_out <= "0001";
 27                 when X"0004" => binary_out <= "0010";
 28                 when X"0008" => binary_out <= "0011";
 29                 when X"0010" => binary_out <= "0100";
 30                 when X"0020" => binary_out <= "0101";
 31                 when X"0040" => binary_out <= "0110";
 32                 when X"0080" => binary_out <= "0111";
 33                 when X"0100" => binary_out <= "1000";
 34                 when X"0200" => binary_out <= "1001";
 35                 when X"0400" => binary_out <= "1010";
 36                 when X"0800" => binary_out <= "1011";
 37                 when X"1000" => binary_out <= "1100";
 38                 when X"2000" => binary_out <= "1101";
 39                 when X"4000" => binary_out <= "1110";
 40                 when X"8000" => binary_out <= "1111";
 41                 when others  => binary_out <= "0000";
 42             end case;
 43         end if;
 44     end process;
 45 end architecture;

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