1 -------------------------------------------------------
  2 -- Design Name : decoder_using_case
  3 -- File Name   : decoder_using_case.vhd
  4 -- Function    : decoder using case
  5 -- Coder       : Deepak Kumar Tala (Verilog)
  6 -- Translator  : Alexander H Pham (VHDL)
  7 -------------------------------------------------------
  8 library ieee;
  9     use ieee.std_logic_1164.all;
 10 
 11 entity decoder_using_case is
 12     port (
 13         enable      :in  std_logic;                    --  Enable for the decoder
 14         binary_in   :in  std_logic_vector (3 downto 0);--  4-bit Input
 15         decoder_out :out std_logic_vector (15 downto 0)--  16-bit Output
 16 
 17     );
 18 end entity;
 19 
 20 architecture behavior of decoder_using_case is
 21 
 22 begin
 23     process (enable, binary_in) begin
 24         decoder_out <= X"0000";
 25         if (enable = '1') then
 26             case (binary_in) is
 27                 when X"0"   => decoder_out <= X"0001";
 28                 when X"1"   => decoder_out <= X"0002";
 29                 when X"2"   => decoder_out <= X"0004";
 30                 when X"3"   => decoder_out <= X"0008";
 31                 when X"4"   => decoder_out <= X"0010";
 32                 when X"5"   => decoder_out <= X"0020";
 33                 when X"6"   => decoder_out <= X"0040";
 34                 when X"7"   => decoder_out <= X"0080";
 35                 when X"8"   => decoder_out <= X"0100";
 36                 when X"9"   => decoder_out <= X"0200";
 37                 when X"A"   => decoder_out <= X"0400";
 38                 when X"B"   => decoder_out <= X"0800";
 39                 when X"C"   => decoder_out <= X"1000";
 40                 when X"D"   => decoder_out <= X"2000";
 41                 when X"E"   => decoder_out <= X"4000";
 42                 when X"F"   => decoder_out <= X"8000";
 43                 when others => decoder_out <= X"0000";
 44             end case;
 45         end if;
 46     end process;
 47 end architecture;

  1 -------------------------------------------------------
  2 -- Design Name : decoder_using_with
  3 -- File Name   : decoder_using_with.vhd
  4 -- Function    : decoder using with-select
  5 -- Coder       : Deepak Kumar Tala (Verilog)
  6 -- Translator  : Alexander H Pham (VHDL)
  7 -------------------------------------------------------
  8 library ieee;
  9     use ieee.std_logic_1164.all;
 10 
 11 entity decoder_using_select is
 12     port (
 13         enable      :in  std_logic;                    --  Enable for the decoder
 14         binary_in   :in  std_logic_vector (3 downto 0);--  4-bit input
 15         decoder_out :out std_logic_vector (15 downto 0)--  16-bit output
 16 
 17     );
 18 end entity;
 19 
 20 architecture behavior of decoder_using_select is
 21 
 22 begin
 23     with (binary_in) select
 24     decoder_out <= X"0001" when X"0",
 25                    X"0002" when X"1",
 26                    X"0004" when X"2",
 27                    X"0008" when X"3",
 28                    X"0010" when X"4",
 29                    X"0020" when X"5",
 30                    X"0040" when X"6",
 31                    X"0080" when X"7",
 32                    X"0100" when X"8",
 33                    X"0200" when X"9",
 34                    X"0400" when X"A",
 35                    X"0800" when X"B",
 36                    X"1000" when X"C",
 37                    X"2000" when X"D",
 38                    X"4000" when X"E",
 39                    X"8000" when X"F",
 40                    X"0000" when others;
 41                    
 42 end architecture;

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