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1 //-----------------------------------------------------
2 // Design Name : clk_div
3 // File Name : clk_div.sv
4 // Function : Divide by two counter
5 // Coder : Deepak Kumar Tala
6 //-----------------------------------------------------
7 module clk_div (
8 input wire clk_in,
9 input wire enable,
10 input wire reset,
11 output reg clk_out
12 );
13 //--------------Code Starts Here-----------------------
14 always_ff @ (posedge clk_in)
15 if (reset) begin
16 clk_out <= 1'b0;
17 end else if (enable) begin
18 clk_out <= ! clk_out ;
19 end
20
21 endmodule
You could download file sv_examples here
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