1 <'
  2 // This test case writes into one random location with 
  3 // random data and reads it back to see if it writen and
  4 // read back correctly
  5 import mem_tb_top.e;
  6 extend mem_txgen {
  7 
  8    gen_cmds()@clk is only {
  9     var i : int = 0;
 10     // Genrate the base object for write access
 11     gen mem_object keeping {
 12        it.rd_wr == TRUE;
 13     };
 14     // Drive the test case
 15     mem_driver.drive_mem(mem_object);
 16     wait cycle;
 17     // Read from same address
 18     mem_object.rd_wr = FALSE;
 19     mem_driver.drive_mem(mem_object);
 20     wait [5]*cycle;
 21    };
 22 };
 23 '>

  1 <'
  2 // This test case writes into one random location with 
  3 // random data and reads it back to see if it writen and
  4 // read back correctly
  5 import mem_tb_top.e;
  6 extend mem_txgen {
  7 
  8    gen_cmds()@clk is only {
  9     for {var i : uint = 0; i < 256; i = i + 1} do {
 10       // Genrate the base object for write access
 11       gen mem_object keeping {
 12         it.rd_wr == TRUE;
 13 	it.addr  == i;
 14       };
 15        // Drive the test case
 16       mem_driver.drive_mem(mem_object);
 17       wait cycle;
 18       // Read from same address
 19       mem_object.rd_wr = FALSE;
 20       mem_driver.drive_mem(mem_object);
 21       wait [5]*cycle;
 22      };
 23    };  
 24 };
 25 '>

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